The present invention relates to a method of manufacturing a semiconductor device, and is for contriving a higher degree of integration and a higher performance in an LSI of, for example, a MOS transistor or the like which uses an SOI substrate.
In recent years, in the LSI of the MOS transistor (hereinafter referred to as MOSFET), a higher degree of integration and a higher performance have been demanded, and a structure in which an SOI (silicon on insulator) layer is formed on a semiconductor substrate with a buried oxide layer therebetween, i.e., a MOSFET using an SOI substrate (hereinafter referred to as SOI-MOSFET) has been paid attention to. In the SOI-MOSFET, perfect device separation is achieved by an insulation layer (silicon oxide layer), so that soft errors and latch-up are suppressed, and high reliability can be obtained even in an LSI with a high degree of integration. In addition, since it is possible to reduce junction capacity of a diffusion layer, charging and discharging attendant on switching are suppressed, which is advantageous in view of contriving a higher speed and a lower electric power consumption.
The SOI-MOSFETs as above-mentioned are generally classified into two kinds according to the operation mode. One of the two kinds is a fully depleted SOI-MOSFET with an operation mode in which a depleted layer induced in a body portion beneath the gate electrode reaches the bottom surface of the body portion, i.e., reaches the interface between the body portion and the buried oxide film. The other of the two kinds is a partially depleted SOI-MOSFET with an operation mode in which the depleted layer does not reach the bottom surface of the body portion, and an electrically neutral region remains in the body portion.
FIG. 9 shows a general sectional view of a general fully depleted SOI-MOSFET. In FIG. 9, an SOI substrate 90 provided with an SOI layer 91 on an Si substrate 90a with a buried oxide film 90b therebetween is used, and a plurality of device separation regions 92 are formed on a part on the principal surface side of the SOI substrate 90 at predetermined intervals.
An impurity (impurity for a body portion) for an n-MOS or p-MOS, for example, is implanted into an Si active layer region (SOI layer) 91a located between the device separation regions 92, and a gate electrode 93b is formed on a part of the surface of the Si active layer region 91a (the surface where the body portion is located) with a gate insulation film 93a therebetween.
In addition, an impurity is implanted into the Si active layer region 91a by use of the gate electrode 93b as a mask, whereby extension portions 91b located between the source/drain portions and the body portion (located beneath side walls 93c which will be described later), i.e., the extension portions 91b in the source/drain portions are formed.
Thereafter, the side walls 93c are formed on the side wall sides of the gate electrode 93b. With the side walls 93c as a mask, an impurity is implanted into the source/drain portions of the Si active layer region 91a to form a diffusion layer (a source/drain layer, which is omitted in the figure). Further, a metallic film is built up on the surfaces of the source/drain portions and the surface of the gate electrode 93b, and is thermally treated (annealing treatment) to form a silicide film 94 (and a gate silicide film 93d).
Then, an inter-layer insulation film is formed so as to cover the device separation region 92, the source/drain portions (silicide film 94), the gate electrode 93b (gate silicide film 93d) and the side walls 93c, thereafter contact holes for electrical connection are opened in the portions of the inter-layer insulation film where the source/drain portions (silicide film 94) are located, and a wiring is formed so as to fill up the contact holes, thereby manufacturing a fully depleted SOI-MOSFET. In FIG. 9, symbol 93e denotes a diffusion layer formed on the gate electrode 93b, together with the extension portions 91b, and the inter-layer insulation film, the contact holes and the wiring are omitted in the figure.
In the case of the fully depleted SOI-MOSFET as above-mentioned, in order that an electrically neutral region in the body portion does not remain, a very thin SOI layer must be formed on the oxide film (namely, the buried oxide film) in a uniform thickness, so that the difficulty on the basis of the manufacturing process is increased; however, there is obtained a great merit that the sub-threshold characteristic (S characteristic) among operation characteristics is improved.
Incidentally, in the fully depleted SOI-MOSFET, since the thickness of the depleted layer in the body portion is restricted by the buried oxide film, the depleted electric charge amount is largely reduced as compared with the partially depleted type, and, in place, movable electric charges contributing to the drain current are increased. As a result, a steep S characteristic is obtained, and, in the case of forming a fully depleted SOI-MOSFET in the 0.13 m generation and later generations, for example, the thickness of the SOI layer must be suppressed to be about 30 nm or less.
Namely, according to the fully depleted SOI-MOSFET, even where a very steep S characteristic is obtained, the threshold voltage can be lowered while suppressing the off-leak current, so that a sufficient drain current can be secured even at a low operating voltage, and a device with an extremely low power consumption such as to be capable of operating at a voltage of 1 V or less (and a threshold voltage of 0.3 V or less), for example, can be produced.
Therefore, in the case of manufacturing an LSI of a super-low power consumption device with high degree of integration and high performance in the future, it is important to establish a process which makes it possible to constitute a fully depleted SOI-MOSFET for a very thin (for example, 30 nm or less in thickness) SOI layer.
In the case where the SOI layer is a thin film as above-mentioned, according to the general technology for manufacturing the fully depleted SOI-MOSFET, the body portion in the SOI layer would be thinned, and the source/drain portions and the extension portions would also be thinned. As a result, the sheet resistance in the source/drain portions and the extension portions is raised, i.e., the parasitic resistance of the transistor is raised, thereby lowering the driving capability.
The sheet resistance of the source/drain portions can be sufficiently reduced by forming a silicide film as shown in FIG. 9, but, as for the sheet resistance of the extension portions, it is necessary to raise the impurity concentration (for example, to about 1×1015/cm2) in the extension portions. When the impurity concentration in the extension portions is raised, however, the extension portion on the source side would be heavily influenced by the electric field (electric line of force) imposed from the drain side, and, particularly in the case where the transistor constituted has a small gate length, the threshold voltage (absolute value of the threshold voltage) is steeply lowered (roll-off characteristic is worsened).
As a method of improving the roll-off characteristic, there is known a method in which, as for example indicated by void arrows in a general illustration in FIG. 10 (the same components as those in FIG. 9 are denoted by the same symbols as above, and description thereof is omitted), after the formation of the extension portions 91b an impurity different in polarity from the impurity in the source/drain portions is halo-implanted (halo ion implantation) to thereby form an impurity layer (hereinafter referred to as reverse-characteristic layer) 95 different from the source/drain layer in electrical characteristics so as to cover the surroundings of the extension portions (the lower surface side of the source/drain portions, the lower surface side of the extension portions, and the gate electrode side), thereby shielding the influence of the electric field from the drain side.
The general halo implantation is carried out, for example, by a method in which the arrangement angle of an SOI substrate arranged in an ion implantation apparatus is adjusted so that ions are obliquely implanted at an implantation angle relative to the direction of a normal to the implanted surface (the surface of the Si active layer region, in an embodiment which will be described later) of more than 7°.
However, in the case where the reverse-characteristic layer is formed on the lower surface side (the buried oxide film side) of the extension portions as shown in FIG. 10, particularly in a fully depleted SOI-MOSFET in which p-MOS is formed, there is the problem that the sheet resistance of the extension portions is raised.
Due to the foregoing, in the fully depleted SOI-MOSFET in which a thin film SOI layer is formed, it is impossible to simultaneously achieve an improvement of roll-off characteristic and a reduction in parasitic resistance, and, therefore, it has been impossible to secure a sufficient driving capability.